The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the design methodology process of electronic circuit designs. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance. Signal integrity has become increasingly important. Meanwhile, increased power demand on ever shrunk chip size as well as the inadequacy of the ideal power assumption in conventional analyses further exacerbates the design challenges. Analysis capabilities such as various analyses and/or measurements from an eye diagram or eye pattern and bit error rate (BER) measurements (e.g., eye amplitude, eye crossing amplitude, eye crossing percentage, eye signal-to-noise ratio, quality factor, vertical eye opening, eye height, eye level, etc.) that account for adverse impacts on signal integrity, circuit performance, timing, etc. from, for example, intersymbol interferences (ISI), simultaneous switching noise (SSN) have become increasingly important, especially during the early design stages of electronic systems.
For computer buses such as the 64-bit or the 128-bit double data rate (DDR) bus, all 64 bits for the 64-bit DDR5 bus (or 128 bits for the 128-bit DDR3 bus) would switch simultaneously and thus draw a tremendous amount of current from the power rails and hence cause ripple in the power supply and noise in the net of the bus architecture as well as other victim nets. Comprehensive analysis techniques such as channel analysis have been developed but are primarily limited to serial interfaces (e.g., the universal serial bus or USB, serial advanced technology attachment or SATA bus, peripheral component interface express or PCIe, etc.) On the other hand, parallel interfaces such as the DDR (double data rate) nth-generation synchronous dynamic random-access memory buses (e.g., DDR3, DDR4, etc.) or QDR (quad data rate) buses have been analyzed with the time consuming general circuit simulation techniques such as SPICE or SPICE-like simulations, perhaps due to the non-linearity of the buffers in these parallel interfaces. With the advent of Gigabit range transfers per second (e.g., Gigatransfers per second or GT/s) and significant increase in bandwidth such as 128-bit wide, 192-bit wide, 256-bit wide buses, such general circuit simulation techniques are impractical at best, while being severely limited in the simulation throughout in the number of bits to tens of thousands of bits or low hundreds of thousands of bits at best.
Therefore, there exists a need for characterizing an electronic system design including a parallel interface and analyzing the characterized the electronic system design by using channel analysis techniques.